A. Ladder Switched Capacitor balancing circuit
The basic architecture of the ladder switched capacitor (SC) is shown in Figure 6(a). The corresponding equivalent circuit for the two-cell balancing model is shown in Figure 6(b). Consider the voltage imbalance assumption “VB1 > VB2”, all PWMs for the half-bridge top (S11, S21) and bottom switches (S21, S22) are synchronously Turn-ON and Turn-OFF respectively, during the first half-switching cycle and reverse the PWMs action in the next half. The SC gets a charge from Cell-1 during the first half-cycle, and the same amount discharges to Cell-2 in the next half-cycle. The steady-state waveform of the switched capacitor under charge balancing operation is shown in Figure 6(c).
Figure 6. Ladder switched capacitor balancing topologies
The capacitor voltage varies from VB2 to VB1 exponentially,
$$ v_c(t) = V_{B2} + (V_{B1} - V_{B2}) \left(1 - e^{-\frac{t}{\tau}} \right) $$charging during the first half cycle and discharge exponentially from VB1 to VB2 in next half cycle, where is the time constant of the circuit. The capacitor reaches the maximum and minimum voltages at the end of half the switching cycle. Therefore, the capacitor ripple voltage can be written as
$$ \Delta V_c = V_{B1} - V_{B2} \cdot \frac{ \left(e^{\frac{D T_s}{\tau}} - 1\right) \left(e^{\frac{(1 - D) T_s}{\tau}} - 1\right) }{ e^{\frac{T_s}{\tau}} - 1 } $$This capacitor current can be expressed as
$$ I_c = \frac{\Delta Q}{T_s} = C \cdot \frac{\Delta V_c}{T_s} $$This average current further participates in balancing the cells. In general, the battery current can be written as
$$ I_{B_i} = \begin{cases} D I_{C_{i-1}} & i = N \\ D I_{C_{i-1}} + (1 - D) I_{C_i} & \forall i = 2, \ldots, N - 1 \\ (1 - D) I_{C_i} & i = 1 \end{cases} $$The SC is designed based on the ripple voltage , and the cell current that transfers the charge from one to another. The simulation result for a six-cell series module with ladder SC balancing is shown in Figure 7.
Figure 7. Voltage balancing results for ladder SC architecture
B. Flying Single Switched Capacitor Balancing Circuit (FSSC)
The operation of the circuit is that the capacitor takes charge from the higher-charge cell and delivers it to the lower-charge cell. Unlike the Ladder SC, this circuit has a transfer path that allows charge to move from any cell to others by controlling the switch matrix, as shown in Figure 8.
Figure 8. Flying single switched capacitor balancing topologies
Considering the imbalance assumption of VB4 > VB2, in the first half of the switching cycle, SB3, SB2, S5, and S4 are Turn-ON where the capacitor gets charged from B4, as shown in Figure 8(b). Similarly, in the next half cycle S5, S4, SB3, and SB2 Turn-ON to transfer the stored charge of the FSSC to B2. A similar operation will be applied for other cases of cel imbalance. Hence it requires a sophisticated control algorithm to control the charge flow from one cell to another. If not, the cell could short-circuit, potentially causing damage to the MOSFETs and the cells themselves. The charge transfer rate is N times greater than that of the ladder circuit because it transfers current from only one cell to another cell. The current delivered by the cells is given by IBi = ICi, where i = 1, 2, ..., N.
C. Chain Structured Switched Capacitor Balancing Circuit
The drawback of the Ladder SC is overcome by adding an FSSC between the extreme ends of the battery pack, given as the chain-structured SC, which is shown in Figure 9. The operation and control of the circuit are quite similar to the ladder SC. The transfer mechanism between the extreme ends is directly controlled by the switches SA11, SA12, SB11, and SB12. The current delivered by the cells is given by
$$ I_{B_i} = \begin{cases} D (I_{C_A} + I_{C_{i-1}}) & \text{for } i = N \\ D I_{C_i} + (1 - D) I_{C_{i-1}} & \forall i = 1, 2, \ldots, N - 1 \\ (1 - D)(I_{C_i} + I_{C_A}) & \text{for } i = 1 \end{cases} $$The simulated balancing operation for a six-cell series module using chained SC is shown in Figure 10.
D. Double-Tiered Switched Capacitor Balancing Circuit
To improve the balancing time of the charge balancing operation, the current distribution among the cells needs to be increased. This can be achieved by parallel/layered architecture. So, an additional layer of the SC network is added to the ladder SC architecture to create the double-tiered switched capacitor (DTSC) architecture, as shown in Fig. 11. The basic operation principle of the DTSC is similar to the ladder SC. However, the current delivered by the cells is given by
$$ I_{B_i} = \begin{cases} D \left(IC_{i-1} + IC_{(i-2,\,i-1)}\right) & i = N \\ D \left(IC_{i-1} + IC_{(i-2,\,i-1)}\right) + (1 - D)\left(IC_i + IC_{(i-1,\,i)}\right) & \forall i = 2, \ldots, N - 1 \\ (1 - D)\left(IC_i + IC_{(i-1,\,i)}\right) & i = 1 \end{cases} $$
The simulation results for the DTSC ACB circuit are shown in Figure 12. It is observed that the time taken to balance the cell voltages is 20.23 sec, which is improved from the ladder and chain structure. The maximum voltage rating of the second layer capacitor of the DTSC network is Vcap_max = 2xVcell.
E. Series-Parallel Switched Capacitor (SPSC) Balancing Circuit
The SPSC circuit can be operated in many ways, shown in Figure 13(a). Conventionally, all the battery-side switches SAi1, SAi2 are Turn-ON and the other switches SBi1, SBi2 are Turn-OFF during the first half cycle, as shown in Figure 13(b). Thus, all the SCs are connected to the respective cells. The charge is transferred from cells to SCs. All the switches SAi1, SAi2 are now turned OFF and other switches ‘SBi1, SBi2’ are turned-on in the following switching cycle, as shown in Figure 13(c). Now, all the capacitors are connected in parallel. The charge was distributed among all the capacitors during this period and settled at the average voltage.
In the next half-cycle, the distributed charge transfers from the capacitor to the cell where the capacitor voltage is higher. Similarly, the capacitor gets charged where the cell voltage is higher. This process will continue until all the cell voltages come under the balanced voltage limits. The variation in the capacitor's voltage is between the cell voltage and average voltage. Hence, the ripple voltage experienced by the capacitors is half of the Ladder SC network ripple voltage. The simulation results for the SPSC ACB circuit are shown in Fig. 14.
The simulation results for the DTSC ACB circuit are shown in Figure 12. It is observed that the time taken to balance the cell voltages is 20.23 sec, which is improved from the ladder and chain structure. The maximum voltage rating of the second layer capacitor of the DTSC network is Vcap_max = 2xVcell.
F. Coupling Capacitor and Star Switched Capacitor Balancing Circuit
There is no direct charge transfer from one cell to another except in FSCC. Therefore, to overcome the serial charge transfer mechanism, a direct/multiple charge transfer path is established between the cells by realizing the SC network into a coupling capacitor and star structure. One end of all the capacitors is connected to the switch node point of the half-bridge module, and the other ends are connected to make the star point, as shown in Figure 15(a). In practice, there is an imbalance in the capacitor voltages due to the unequal ESR of the SC and the circuit path resistance. Therefore, the star node is connected to any battery pack terminal to get stable voltages among the capacitors. This arrangement can be seen in Figure. 16(a). Suppose any of the cell voltages obey voltage band limits; then the PWMs are Turn-Off for the corresponding cell's SCs. This minimizes the energy loss, which can be achieved by improving the control algorithm. These advantages cannot be achieved in the series charge transfer mechanism.
The capacitor voltages under the steady-state operation for the coupled SC network are given by
$$ VC_i = \sum_{j=1}^{i} \frac{(VB_j - VB_i)^2}{2} \quad \forall i = 1, 2, \ldots, N $$
The capacitor voltages under the steady-state operation for the Star SC network are given by
$$ VC_i = \begin{cases} \sum_{j=1}^{N/2} \frac{(VB_j - VB_i)^2}{2} & \forall i = 1, 2, \ldots, N/2 \\ \sum_{j=N/2+1}^{i} \frac{(VB_i - VB_j)^2}{2} & \forall i = N/2+1, \ldots, N \end{cases} $$
G. Delta and Mesh Switched Capacitor Balancing Circuit
The faster charge-balancing operation can be enabled by increasing the layer of the SC network. The delta and mesh SC balancing circuits have been developed to achieve the fast balancing, as shown in Figures 17(a) & 18(a), respectively. The Delta SC ACB is an extended version of DTSC and has more charge transfer paths than DTSC. However, it does not have the direct charge transfer path from one cell to another. In the same way, the mesh SC architecture will balance charges faster than other circuits because it has both series and parallel charge transfer paths. The voltage balancing results for both SC networks are shown in Figures 17(b) & 18(b), respectively.
The comparison of different switched capacitor balancing circuits is given below.
Switched Capacitor Topology | No. of Switches | No of Capacitor | Control Complexity | Charge Transfer Path | Ideal |
Ladder FC Chain Structure | 2N N+5 2N+4 | N-1 1 N | Simple Complex Simple | Series Series & Parallel Series | Vcell |
DISC Series-Parallel | 2N 4N | N+6 N | Simple | Series | 2*Vcell Vcell |
CC SC | 2N | N | Simple | Parallel | N*Vcell |
STAR | 2N | N-1 | Simple | Parallel | ((N+1)/2)* Vcell |
Delta[ Mesh | 2N | N(N-1)/2 2N | Simple | Series & Parallel | (N-1)* Vcell |
Conclusion
The design of an active charge balancing system aims to achieve faster operation, high efficiency, and cost-effectiveness. Faster balancing can be implemented using parallel or multiple paths in switched capacitor (SC) architectures. However, these architectures typically support balancing currents of less than one ampere, limiting their application to low-power battery packs, generally below 0.5 kW.
Frequently Asked Questions:
1. How does the Ladder SC balancing circuit work?
In Ladder SC, charge is moved step by step from one cell to the next using capacitors. It is simple and easy to control but can be slower because charge moves in series.
2. What is the Flying Single Switched Capacitor (FSSC) circuit?
FSSC allows direct charge transfer between any two cells using a switch matrix. It is faster than Ladder SC but needs more complex control to avoid short circuits.
3. What is the Chain Structured SC circuit?
The Chain SC combines Ladder SC with FSSC connections between the pack’s extreme ends. This improves performance by giving an extra path for charge transfer.
4. What is the Double-Tiered SC (DTSC) circuit?
DTSC adds a second SC layer on top of the Ladder SC. This increases balancing current and reduces balancing time, making it faster than Ladder or Chain SC.
5. What is the Series-Parallel SC (SPSC) circuit?
SPSC connects capacitors in series during charging and then in parallel during discharging. This helps share charge more evenly and reduces capacitor stress.